Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.
GENISSNX allows you to promote efficiency process at IC package design phase. This product has ERC Function (Electrical Rule Check) function (GENISSNX ERC Function) to check if there are electrical problems in the routed design data, and high speed and accuracy layer count estimator including outline trace generator （GENISSNX WB Function/FC Function） which enable to provide optimized connection information within IC package based on auto-routing technology.
ERC Function (Electric Rule Check) function detects electric characteristics problems caused by IC package.
Reporting ERC Function result considered electric characteristics like EMI or associated design information needed to pay attention electrically supports your high quality IC package development.
World's first tool that auto-computes the layer count of IC package (FCBGA), and optimum connectability between chip pads and packages pins. Comprehensive support for IC package design flow in IC development.
GENISSNX
CAD (APD) link option from CADENCE
TAT: Turn Around Time
LSIPKG: LSI Package
FCBGA: Flip Chip Ball Grid Array
SiP: System in Package
Please click the "Contact" button below to ask questions about our products and solutions.
NEC Informatec Systems's Privacy Policy is here. Please note that, by sending an inquiry to us, you acknowledge acceptance of the policy.
