Previous events

IEEE EMC Symposium 2008 in Detroit

We will be exhibiting newly released EMIStream V3.10 which offers optional high performance SPICE engine and the new version of PIStream, a power integrity control support tool at IEEE2008.
Please stop by the NEC Baseball Park and enter to win a Wii!


Venue: Cobo Center in Detroit MI, USA
Open: Aug 19 – 21, 2008
Booth# 726

Seminar in Detroit

-Noise Control for Real-World PCB Design -


Date: Aug 21, 2008
Time: 15:30 – 18:30
Venue: Marriott Hotel Detroit

[Speakers]
Prof. Todd Hubing (Clemson University)
Laying out the "Ground" in a Mixed Analog/Digital Circuit Board Design
PhD. Takashi Harada (NEC Lab.)
Chip-Package-Board Co-design applying LSI Power-pin Model
Eriko Yamato (TechDream, Inc)
Introduction of EMIStream and PIStream
EMIStream User Testimonial - Success story by SI/EMC Engineer

Abstract:

Laying out the "Ground" in a Mixed Analog/Digital Circuit Board Design

Prof. Todd Hubing Problematic printed circuit board layouts are often the result of somebody trying to comply with EMC design rules related to the routing of "ground" in mixed analog/digital boards. It is important to remember that the planes and traces in a circuit board that are labeled "ground" often serve two purposes. Ground planes are designed to provide a zero potential reference for the signals on the board; and they are part of the signal current path. Unfortunately, the accepted rules for laying out ground conductors and signal current conducts often conflict with one another. This presentation reviews grounding concepts that are particularly important when designing a mixed-signal circuit board. It also discusses methods for meeting all signal path requirements while ensuring that the ground structure provides a stable and quiet, zero-potential reference.

Chip-Package-Board Co-design applying LSI Power-pin Model

PhD. Takashi Harada A fast board-power-voltage fluctuation analysis system to realize the chip-package-board co-design is presented. To reduce the time loss by the rework and increase circuit design efficiency, short turnaround-time estimation techniques for analyzing the signal integrity and the power integrity of integrating chip-package-board characteristics have been required. This system contributes to the increase of design efficiency in the early product development stage.

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